Pey Kin Leong

Associate Provost, Science and Math Cluster Lead

Email: crlxvayrbat@fhgq.rqh.ft
Website: http://people.sutd.edu.sg/~peykinleong/
Telephone: +65 6303 6617
Research Areas:
Electrical Engineering

Pillar / Cluster: Engineering Product Development, Science and Math

Biography

Dr. Pey Kin Leong received his Bachelor of Engineering (1989) and Ph.D (1994) in Electrical Engineering from the National University of Singapore. He has held various research positions in the Institute of Microelectronics, Chartered Semiconductor Manufacturing, Agilent Technologies and National University of Singapore. He was previously Head of the Microelectronics Division, Program Director of the Si Technology Research group, Laboratory Supervisor of the Micro Fabrication Facility, and the Director of the Microelectronic Center in the School of Electrical & Electronics Engineering, Nanyang Technological University, Singapore, and holds a concurrent Fellowship appointment in the Singapore-MIT Alliance (SMA).

Dr. Pey is a senior member of IEEE and an IEEE EDS Distinguished Lecturer, and has been the organizing committee member of IPFA since 1995. He was the General Chair of IPFA2001, Singapore and the co-General Chair of IPFA2004, Hsinchu, Taiwan. KL Pey was the Guest Editor of IEEE Transactions on Devices in and Materials Reliability in 2003-05 and 2007, and the Chair of the Singapore IEEE REL/CPMT/ED Chapter in 2004/05, and served on the 2006/07/08 IRPS technical subcommittee, and the IPFA’02 to IPFA’06 and IPFA’08 technical committee, and the 2007 IEDM CMOS & Interconnect Reliability and 2008 IEDM Characterization, Reliability and Yield sub-committee.
Dr. Pey has published more than 185 international refereed publications (including 7 invited papers and one review article) and 159 technical papers at international meetings/conferences (including 24 invited talks and 17 papers in IEDM/IRPS), and holds 34 US patents. Dr. Pey has contributed significantly to the CMOS gate dielectric reliability, especially in the areas of physical analysis of ultra-thin dielectric breakdown mechanism.

Education

  • 1994:  Ph.D, Department of Electrical Engineering, National University of Singapore
  • 1989:  B.Eng. (First Class Honors), Department of Electrical Engineering, National University of Singapore

Research Interest

  • Cu interconnectsand low-k materials reliability.
  • Physical analysis of gate dielectric breakdown.
  • Pulsed laser annealing for transistor engineering.
  • Nanosilicided hetero-junction wire and III-V nanowires for MOSFETs.
  • Nanowire-based devices for computational, memory, microbattery, photovoltaic and bio-applications.

Awards and Achievements

  • 2011 IEEE Electron Devices Society PhD Student Fellowship: Mr. Nagarajan Raghavan for his PhD work.
    TSMC 2010 Outstanding Student Research Award: Ms. Wu Xing for her work on “Physical Analysis of Breakdown in Advanced High-k Gate Dielectric Using Transmission Electron Microscopy and Atomistic Simulations”.
  • The 1st place in photo contest for “Art of Failure Analysis” of the 17th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2010).
  • IEEE 2009 International Physical and Failure Analysis Symposium Best Paper (Reliability) award.
  • 2009 The Electrochemical Society Norman Hackerman Young Author Award in Solid-State Science & Technology for PhD student Tan Eujin’s paper entitled, “Materials and Electrical Characterization of Er(Si1-xGex)2-y Films Formed on Si1-xGex(001) (x = 0-0.3) via Rapid Thermal Annealing”.
  • Japan Society for the Promotion of Science (JSPS), Visiting Professor, Tokyo Institute of Technology, 2 Feb – 7 Feb 2009.
  • TSMC 2008 Outstanding Student Research Award:
    o. A Commendation Prize in Category III: Physics, Chemistry of Material for Nano-Scale Devices by Mr. Li Xiang for his work on “Gate dielectric reliability study using TEM and EELS.
    o. A Bronze Prize in Category III: Physics, Chemistry of Material for Nano-Scale Devices by Ms Ong Yi Ching on “Scanning Tunneling Microscopy of the Sc2O3/La2O3/SiOx Gate Stack – A Nanoscopic Perspective”.
  • Paper on “The Chemistry of Gate Dielectric Breakdown” by X Li, CH Tung, KL Pey and V. Lo was selected as a highlight at the IEEE 2008 Electron Device Meeting, San Francisco, USA.

Selected Publications

  • K. L. Pey, N. Raghavan, X. Li, W. H. Liu, K. Shubhakar, X. Wu, and M. Bosman, “New insight into the TDDB and breakdown reliability of novel high-kgate dielectric stacks”, presented at the Reliability Physics Symposium, IEEE International (IRPS), (invited paper), 2010.
  • N. Raghavan, K. L. Pey, W. H. Liu, X. Wu, and X. Li, “Unipolar recovery of dielectric breakdown in fully silicided high- κ gate stack devices and its reliability implications”, Applied Physics Letters 96, 142901 (2010).
  • X. Wu, K. Li, N. Raghavan, M. Bosman, Q. X. Wang, D. Cha, X. X. Zhang, and K. L. Pey, “Uncorrelated multiple conductive filament nucleation and rupture in ultra-thin high-k dielectric based resistive random access memory”, Applied Physics Letters 99, 093502 (2011). (Also selected to be published in the Virtual Journal of Nanoscale Science and Technology, Sept’11 Issue)
  • E.J. Tan, K.L. Pey, D.Z. Chi, P.S. Lee, and L.J. Tang, “Improved electrical performance of erbium silicide Schottky diodes formed by pre-RTA amorphization of Si”, IEEE Electronic Device Letters, Vol. 27, no. 2, Feb 2006, pp. 93-95.
  • X. Li, C.H. Tung, K.L. Pey, V.L. Lo, “The chemistry of gate dielectric breakdown”, IEEE IEDM Tech. Dig., pp. 779-782, 2008.
  • R. Ranjan, K.L. Pey, C.H. Tung, L.J. Tang, G. Groeseneken, L.K. Bera and S. De Gendt, “ A Comprehensive Model for Breakdown Mechanism in HfO2 High- k Gate Stacks”, IEEE IEDM Tech. Dig., pp. 725 – 728, 2004.
  • K.L. Pey , V.L. Lo, C.H. Tung, W. Chandra, L.J. Tang, D.S. Ang, R. Ranjan, “New insight into gate dielectric breakdown induced MOSFET degradation by novel percolation path resistance measurements”, IEEE IEDM Tech. Dig., pp. 717 – 720, 2004