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Yeo Kiat Seng

Associate Provost, Research & International Relations

Email: 
Website: http://people.sutd.edu.sg/~kiatseng_yeo/
Telephone: +65 6499 4895
Research Areas:
Electrical Engineering

Pillar / Cluster: Engineering Product Development

Biography

Associate Provost for International Relations and Graduate Studies, Professor Yeo Kiat-Seng joined Singapore University of Technology and Design (SUTD) on 2nd July 2014. He has over 25 years of experience in industry, academia and consultancy. Before his appointment at SUTD, he was Full Professor at Nanyang Technological University (NTU), Singapore, and spent 13 years in management positions as Associate Chair (Research), Head of Circuits and Systems and Sub-Dean (Student Affairs) in the School of Electrical and Electronic Engineering (EEE). As Associate Chair (Research), he developed EEE mega research centres into a top-notch hub to advance cutting-edge research innovations and unparalleled inventions. Prof. Yeo was also a Fellow of the Renaissance Engineering Programme (REP) and served as Senator and Advisory Board Member at NTU. Besides, he was the Founding Director of VIRTUS, a S$50 million IC Design Centre of Excellence jointly set up by NTU and Singapore Economic Development Board. Since 1996, he has been providing consultancy services to statutory boards, local SMEs and multinational corporations in the areas of electronics and IC design.

Currently, Prof. Yeo is a Visiting Professor in the School of EEE at NTU, a Member of Board of Advisors of the Singapore Semiconductor Industry Association, a Council Member of the Assembly & Test WSQ Framework Industry Skills and Training of the Singapore Workforce Development Agency, a Member of the Engineering Science (ES) Advisory Committee of Ngee Ann Polytechnic and a Member of Hwa Chong Institutional IP Advisory Board.

Prof. Yeo is a world-renowned authority on low-power RF/mm-wave IC design and a recognized expert in CMOS technology. He has secured over S$30 million of research funding from various funding agencies and the industry in the last 3 years. He is the author of 6 books and 5 book chapters. The 6 books are: Intellectual Property for Integrated Circuits (J. Ross Publishing (USA), 2010), Design of CMOS RF Integrated Circuits and Systems (World Scientific Publishing, 2010), Low-Voltage, Low-Power VLSI Subsystems (McGraw-Hill, New York, 2005), Low-Voltage Low-Power Digital BiCMOS Circuits: Circuit Design, Comparative Study, and Sensitivity Analysis (Prentice Hall, 2000) and CMOS/BiCMOS ULSI: Low-Voltage, Low-Power (Prentice Hall, 2002). The latter was translated to Chinese version and became an ever popular foreign textbook in China. In addition, he has published over 500 international top-tier refereed journal and conference papers in his area of research and holds 35 patents, including 2 patents for the world’s smallest integrated transformer, a patent for the world’s smallest integrated filter for 60GHz standard, the inventor of several high Q-factor RF spiral inductors and co-inventor of quite a few novel circuit techniques for RF/mm-wave IC applications.

Prof. Yeo has supervised or trained more than 100 researchers and postgraduate students, many of whom are successful leaders in the industry and academia. He gave several keynotes and invited talks at various scientific conferences, meetings, workshops and seminars. Furthermore, he serves in the editorial board of IEEE Transactions on Microwave Theory and Techniques and was one of the Guest Editors of Journal of Circuits, Systems and Computers on Green Integrated Circuits and Systems from 2008 to 2010 and on Energy and Variability Aware Circuits and Systems from 2011 to 2013. Prof. Yeo also holds/held key positions in many international conferences as Advisor, General Chair, Co-General Chair and Technical Chair. In 2009, he was conferred the Public Administration Medal (Bronze) on National Day by the President of the Republic of Singapore and the distinguished Nanyang Alumni Award by NTU for his outstanding contributions to the university and society.

Education

  • PhD Nanyang Technological University 1996
  • BEng(Elect.)(Hons) Nanyang Technological University 1993

Research Interests

  • Low-power IC Design
  • Internet of Things
  • Visible Light Communications
  • CMOS Technology
  • RF/mm-wave IC Design

Awards and Achievements

  • 9 August 2009, National Day Award: The Public Administration Medal (Bronze) [PINGAT PENTADBIRAN AWAM (GANGSA)] awarded by the President of Republic of Singapore for outstanding efficiency, competence and industry.
  • 24 October 2009, Nanyang Alumni Achievement Award in recognition of his exemplary achievements in research.
  • 30 August 2012, Singapore Infocomm Technology Federation (SiTF) 2012 ‘Special Mention’ Award under Emerging Technologies Category Awards for Singapore’s Next Generation WiFi Chipset.

Selected Publications

  • A.T. Do and K. S. Yeo, “A Hybrid NEO-Based Spike Detection Algorithm for Implantable Brain-IC Interface Applications” accepted in IEEE International Symposium on Circuits and Systems (ISCAS 2014), Melbourne, Australia, 2014.
  • Kaixue Ma, S. Mou, Y. Wang, J. Yan, K. S. Yeo, “A Miniaturized 28mW 60GHz Differential Quadrature Sub-Harmonic QPSK Modulator in 0.18um SiGe BiCMOS,” IEEE IMS 2014, Tampa Bay, Florida, USA (accepted).
  • N. Mahalingam, Y. Wang, Kaixue Ma,  K. S. Yeo, S. Mou, “A 24 GHz Low Power Low Phase Noise Dual-Mode Phase locked Loop Frequency Synthesizer for 60 GHz Applications,” IEEE IMS 2014, Tampa Bay, Florida, USA (accepted).
  • B. K. Thangarasu, Kaixue Ma, K. S. Yeo, W. M. Lim, “A 35 mW 30 dB Gain Control Range Current Mode Programmable Gain Amplifier With DC Offset Cancellation,” IEEE IMS 2014, Tampa Bay, Florida, USA (accepted).
  • Kaixue Ma, Shouxian Mou, Nagarajan Mahalingam, Yisheng Wang, Bharatha Kumar Thangarasu, Jinna Yan, Wanxin Ye, Keping Wang, Wei Meng Lim, Thin Sek Wong, Yang Lu, Wanlan Yang, Kiat Seng Yeo, Francois Chin, Xiaoming Peng, Albert Chai, Khiam-Boon Png, Wong Sai Ho, Raymond Keh, Cai Zhaohui, Zhang Guoping, Chee Piew Yoong, Yin Jee Khoi, Zhang Weiqiang, Qu Xuhong, Law Sie Yong, Zhao Cheng, Chen Jian Simon, Cheng Wang Cho, Raymond Jayaraj Jin Bo, Mei Sun, Xianmin Qing and Zhining Chen, “An Integrated 60GHz Low Power Two-Chip Wireless System Based on IEEE802.11ad Standard,” IEEE IMS 2014, Tampa Bay, Florida, USA (accepted).
  • Wen Lin Xu, Xiao Peng Yu, Wei Meng Lim, and Kiat Seng Yeo, “Special Issue on Nanoelectronics Design and Optimization of a Milli-Meter Wave Amplifier using Nano-Scale CMOS Devices,” accepted for publication in Nanoscience and Nanotechnology Letters. (May 2014).
  • Boyu Hu, Xiao Peng Yu, Wei Meng Lim and Kiat Seng Yeo, “Analysis and Design of Ultra-Wideband Low-Noise-Amplifier With Input/Output Bandwidth Optimization and Single-Ended/Differential Input Re-Configurability”, IEEE Transactions on Industrial Electronics, vol.pp, no.99, April 2014.
  • Kaixue Ma, Ningning Yan, Kiat Seng Yeo, and Wei Meng Lim, “Miniaturized 40-60GHz On-Chip Balun with Capacitive Loading Compensation,” in IEEE Electron Device Letters, Vol. 35, No. 4, pg. 434-436, Apr 2014.
  • Anh Tuan Do, Chun Yin, Kavitha Velayudhan, Zhao Chuan Lee, Kiat Seng Yeo and Tony Tae-Hyoung Kim, “0.77 fJ/bit/search Content Addressable Memory Using Small Match Line Swing and Automated Background Checking Scheme for Variation Tolerance” Accepted for publication in IEEE Journal of Solid-State Circuits, March 2014.
  • M. Nagarajan, Kaixue Ma, Kiat Seng Yeo, “Coupled Dual LC Tanks based ILFD with Low Injection Power and Compact Size,” IEEE MWCL, vol.24, no.2, pp.105-107, Feb 2014.
  • F. Meng, Kaixue Ma, K. S. Yeo, Shanshan Xu, Chirn Chye Boon, and Wei Meng Lim, “Miniaturized 3-bit phase shifter for 60 GHz phased-array in 65 nm CMOS technology,” IEEE MWCL, vol.24, no.1, pp.50-52, Jan 2014.
  • Chen Feng, Xiao Peng Yu, Wei Meng Lim, and Kiat Seng Yeo, “A Compact 2.1-39 GHz Self-Biased Low-Noise Amplifier in 65nm CMOS Technology,” in IEEE Microwave and Wireless Components Letters, Vol. 23, No. 12, pg. 662-664, Dec 2013.
  • Nagarajan Mahalingam, Ma Kaixue, Yeo Kiat Seng, and Lim Wei Meng, “K-band High-PAE Wide-Tuning-Range VCO Using Triple-Coupled  LC Tanks”, IEEE Transactions on Circuits and Systems II, vol. 60, no. 11, pp. 736 – 740, Nov 2013.
  • M. Nagarajan, Kaixue Ma, Kiat Seng Yeo, “A K-band High PAE Wide Tuning Range VCO Using Triple-Coupled LC Tanks,” IEEE Transactions on CAS-II., vol.60, no.11, pp. 736-740, Nov 2013.
  • Hao Yu, Wei Fei, Haipeng Fu, Junyan Ren, and Kiat Seng Yeo, “Design and Analysis of Wide Frequency-tuning-range CMOS 60GHz VCO by Switching Inductor Loaded Transformer”, IEEE Transactions on Circuits and Systems I, vol. PP, no. 99, pp. 1-13, Oct 2013.
  • Loo Xi Sung, Yeo Kiat Seng, and Chew Kok Wai J., “THRU-Based Cascade De-embedding Technique for On-Wafer Characterization of RF CMOS Devices”, IEEE Transactions on Electron Devices, vol. 60, no.9, pp. 2892-2899, Sep 2013.
  • Ma Kaixue, Mou Shouxian, Wang Keping and Yeo Kiat Seng, “Embedded Transformed Radial Stub Cell for BPF With Spurious-Free Above Ten Octaves”, IEEE Transactions on Components Packaging and Manufacturing Technology, vol. 3, no. 9, pp. 1597-1603, Sep 2013.
  • Anh Tuan Do, Chun Yin, Kiat Seng Yeo and Tony Tae-Hyoung Kim, “Design of a Power-Efficient Cam Using Automated Background Checking Scheme for Small Match Line Swing”, 2013 European Solid-State Device Research & 2013 European Solid-State Circuits Conference (ESSDERC/ESSCIRC 2013), Bucharest, Romania, pp. 209-212, 16-20 Sep 2013.
  • Anh Tuan Do, Jayaraman Karthik Gopal, Pushpapraj Singh, Chua Geng Li, Kiat Seng Yeo and Tony Tae-Hyoung Kim, “A Cantilever-Based Non-Volatile Memory Utilizing Vibrational Reset for High Temperature Operation”, 2013 European Solid-State Device Research & 2013 European Solid-State Circuits Conference (ESSDERC/ESSCIRC 2013), Bucharest, Romania, pp. 244-287, 16-20 Sep 2013.
  • Chun Kit Lam, Meng Tong Tan, Stephen M. Cox, Kiat Seng Yeo, “Class D Amplifier Power Stage with PWM Feedback Loop”, IEEE Transactions on Power Electronics, vol. 28, no. 8, pp. 3870 – 3881, Aug 2013.
  • Kaixue Ma, Shouxian Mou and Kiat Seng Yeo, “Miniaturized 60-GHz On-Chip Multimode Quasi-Elliptical Bandpass Filter”, IEEE Electron Device Letters, vol. 34, no. 8, pp. 945 – 947, Aug 2013.
  • Kaixue Ma, Shouxian Mou, Kiat Seng Yeo, “A Miniaturized 60GHz On-chip Multimode Elliptical Bandpass Filter,” IEEE Electronic Devices Letter, vol.34, no.8, pp.945-947, Aug 2013.
  • Thangarasu Bharatha Kumar, Kaixue Ma, and Kiat Seng Yeo, “Temperature Compensated dB-linear Digitally Controlled Variable Gain Amplifier with DC Offset cancellation”, IEEE Transactions on Microwave Theory and Techniques, vol. 61, no. 7, pp. 2648-2661, Jul 2013.
  • Yang Shang, Hao Yu, Deyun Cai, Junyan Ren, and Kiat Seng Yeo, “Design of High-Q Millimeter-Wave Oscillator by Differential Transmission Line Loaded With Metamaterial Resonator in 65-nm CMOS”,  IEEE Transactions on Microwave Theory and Techniques, vol. 61, no. 5, pp. 1892-1902,  May 2013.
  • Ma Kaixue, Mou Shouxian, and Yeo Kiat Seng, “A Miniaturized Millimeter-Wave Standing-Wave Filtering Switch with High P1dB”, IEEE Transactions on Microwave Theory and Techniques, vol. 61, no. 4, pp. 1505-1515, Apr 2013.
  • Loo, X. S.; Yeo, K. S.; Chew, K. W. J.; Chan, L. H. K.; Ong, S. N.; Do, M. A.; Boon, C. C., “A New Millimeter-Wave Fixture De-embedding Method Based on Generalized Cascade Network Model”, IEEE Electron Device Letters, vol. 34, no. 3, pp. 447-449, Mar 2013.
  • Wei Fei, Hao Yu, Yang Shang, and Kiat Seng Yeo, “A 2D Distributed Power Combining by Metamaterial-based Zero-Phase-Shifter for 60GHz Power Amplifier in 65nm CMOS”, IEEE Transactions on Microwave Theory and Techniques, vol. 61, no. 1, pp. 505-516, accepted Feb 2013.
  • Deyun Cai, Haipeng Fu, Junyan Ren, Wei Li, Ning Li, Hao Yu, and Kiat Seng Yeo, “A Dividerless PLL with Low Power and Low Reference Spur by Aperture-Phase Detector and Phase-to-Analog Converter”, IEEE Transactions on Circuits and Systems I (TCAS-I), vol. 60, no. 1, pp. 37-50, Jan 2013.
  • Yeo Kiat Seng, Do Manh Anh and Boon Chirn Chye, “Design of CMOS RF Integrated Circuits and Systems,” World Scientific Publishing (Singapore), International Edition, no. of pages 360, ISBN 978-981-4271-55-4, 981-4271-55-1, Mar 2010.
  • Yeo Kiat Seng, Ng Kim Tean, Kong Zhi Hui, and Tricia Dang Bee Yoke, “Intellectual Property for Integrated Circuits,” J. Ross Publishing (USA), International Edition, no. of pages 216, ISBN 978-1-932159-85-1, Jan 2010.
  • Yeo Kiat Seng and Kaushik Roy, “Low-Voltage, Low-Power VLSI Subsystems” McGraw-Hill, New York, International Edition, 2005. ISBN 0-07-143786-X, Dec 2005.
  • Yeo Kiat Seng, Samir S. Rofail and Goh Wang Ling, “CMOS/BiCMOS ULSI: Low-Voltage Low-Power,” (Chinese Edition) Prentice-Hall, ISBN 7-5053-8712-X, Dec 2003.
  • Yeo Kiat Seng, Samir S. Rofail and Goh Wang Ling, “CMOS/BiCMOS ULSI: Low-Voltage Low-Power,” Prentice-Hall, Upper Saddle River, New Jersey 07458, Professional Technical Reference, International Edition, ISBN 0-13-032162-1, Dec 2002.
  • Samir S. Rofail and Yeo Kiat Seng, “Low-Voltage Low-Power Digital BiCMOS Circuits: Circuit Design, Comparative Study and Sensitivity Analysis,” Prentice-Hall, Upper Saddle River, New Jersey 07458, Professional Technical Reference, International Edition, 2000. ISBN 0-13-011380-8, Dec 2000.

Projects

Project Title: Cognitive Sensor with Dual Mode of Operations in High Performance SPAD (Single Photon Avalanche Photo diode) Imager
(Master of Engineering)

Supervisor: Yeo Kiat Seng

Field of Interest: Semiconductors, Analog integrated circuit design and Advance optical sensor process technology, image algorithm and artificial intelligence

Abstract: SPAD sensor development has recently been a very much sought-after topic and new advances in CMOS process technology has enabled the realization of high pixel count 3D imagers using SPAD in the Geiger Mode of operations in a common terminology called Time of Flight (ToF). ToF is simply and optical arrangement whereby a laser light is synchronized with a SPAD sensor and the flight time of light photon from the sensor module to the object and its reflection is precisely measure yielding a depth of distance measurement. However, Avalanche Photodiodes can also be used in the Silicon Photo Multiplier mode in which the sensor can become a very high gain photon detector which is often used in medical imaging.

In this project, the student is required to study the details of both modes of operations of CMOS based SPADs and to investigate the possibility of using such photodiodes in the Geiger Mode as well as in the Silicon Photon Multiplier mode. The results of the device characteristics is the basis for the candidate to propose and develop suitable analog front-end circuitry whereby the sensor information obtained by each mode of operations can be digitalised and provided to the system host image processor for 3D object recognition – cognitive sensor.  A key focus of the front-end development will focus on very low power analog circuitry as well as low power digital processing of the ToF/ Photo-multiplier raw data before providing the information to upper layer applications and algorithms.

Project title: Millimeter-wave Communication Systems for Low-power Applications
(SUTD-CGU Dual Master Program in Nano-Electronic Engineering and Design (NEED))

Supervisor: Yeo Kiat Seng
Co-supervisor: Tan Cher Ming, Chang Gung University (https://en.wikipedia.org/wiki/Chang_Gung_University)

Field of Interest: Semiconductors, RF/mm-wave integrated circuit design and Transceivers

Abstract: A high data-rate millimetre-wave (MMW) wireless communication system for low-power applications is proposed in this PhD research. The system is developed based on a system-on-chip (SoC) MMW transceiver with a Field Programmable Gate Array (FPGA) platform working as a baseband processor and medium access control (MAC) layer. The proposed design focuses on Gigabits-per-second (Gbps) outdoor point-to-point data transfer application for long distance communication. It will provide a full-duplex Gigabit Ethernet interface for the user to access the system. The project can be separated into background study, RF/MMW channel & link budget estimation, system architecture construction, RF/MMW device measurement & non-ideal characteristic compensation, baseband synchronization, channel coding, MAC design, and prototyping.

In this project, the student will design and simulate a low-power MMW transceiver using EDA tools. Throughout this project, the student is expected to accomplish the following tasks:

  • Literature review;
  • Design of MMW transceiver;
  • Paper publication for the work done.

Students who are interested in the area of IC design are strongly encouraged to apply.

Reading materials

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  2. T. S. Rappaport, R. W. Health, Jr., R. C. Daniels, and J. N. Murdock, “Millimeter Wave Wireless Communications”, Englewood Cliffs, NJ, USA: Prentice Hall, 2015.
  3. SK Yong, P. Xia, A. V. Garcia, “60 GHz technology for Gbps WLAN and WPAN, from theory to practice”, A John Wiley & Sons Ltd, UK, 2011.
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  6. R. J. Weiler, M. Peter, W. Keusgen, “Outdoor millimeter-wave access for heterogeneous networks – path loss and system performance”, IEEE 25th Annual Intern. Symp. On personal, indoor, and Mobile Radio Communication (PIMRC), pp. 2189-2193, 2014.
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  23. Analog Devices, “JESD204B Survival Guide, practical JESD204B technical information, tips, and advice from the world’s data converter market share leader”, Analog device technical article, MS-2374. 2013.
  24. Analog Devices, “Quad, 16-bit, 2.8 GSPS, TxDAC+, Digital-to-Analog Converter, data sheet AD9144”, 2017.
  25. Analog Devices, “14-bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter, data sheet AD9680”, 2017.
  26. Xilinx,  “JESD204 V7.1,  LogiCore IP product guide, Vivado design suite”, PG066, June 7, 2017.
  27. N. Saito, et al., “A fully integrated 60-GHz CMOS transceiver chipset based on WiGig/IEEE 802.11ad with build-in self-calibration for mobile usage”, IEEE J. Solid-State Circuits, vol. 48, pp. 3146-3159, Dec. 2013.
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  33. T. Siriburanon et al. ”A low-power low-noise mm-wave subsampling PLL using dual-step-mixing ILFD and tail-coupling quadrature injection-locked oscillator for IEEE 802.11ad,”  IEEE J. Solid-State Circuits, vol.51, no. 11, pp. 2560-2571, Nov. 2015.
  34. K. Okada, “60 GHz WiGig frequency synthesizer using injection locked oscillator”, IEEE RFIC Symp. Dig Paper, Jun. 2012, pp. 76-79.
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  51. Saeid Daneshgar, Kaushik Dasgupta, “A 27.8Gb/s 11.5pJ/b 60GHz Transceiver in 28nm CMOS with Polarization MIMO”, IEEE Intern. Solid-State Circuits Conference (ISSCC), Feb 2018.
  52. Shinwon Kang, Chintan Thakkar, “A 40Gb/s 6pJ/b RX Baseband in 28nm CMOS for 60GHz Polarization MIMO”, IEEE Intern. Solid-State Circuits Conference (ISSCC), Feb 2018.
  53. K. Okada, N.Li, K. matsushita, et al, “A 60-GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiver for IEEE802.15.3c”, IEEE J. Solid-State Circuits, vol.46, No. 12, Dec 2011.
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  55. N. Saito, T. Takayuki, N. Shirakata, et al., “A  Fully Integrated 60-GHz CMOS transceiver chipset based on WiGig/IEEE 802.11ad with build-in  self calibration for mobile usage”, IEEE J. Solid-State Circuits, vol.48, No. 12, December 2013.
  56. K. Okada,  R. Minami, Y. Tsukui, et al., “A 64-QAM 60GHz CMOS transceiver with 4 channel-bonding”, IEEE Intern. Solid-State Circuits Conference (ISSCC), Feb 2014.
  57. R. Wu, R. Minami, Y. Tsukui, et al., “64-QAM 60-GHz CMOS for IEEE 802.11ad/ay”, IEEE J. Solid-State Circuits, vol.52, No. 11, November 2017.
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Project title: A 2.4GHz Ultra-Low-power Radio for Cognitive Cameras
(SUTD-CGU Dual Master Program in Nano-Electronic Engineering and Design (NEED))

Supervisor: Yeo Kiat Seng
Co-supervisor: Tan Cher Ming, Chang Gung University (https://en.wikipedia.org/wiki/Chang_Gung_University)

Field of Interest: Semiconductors, Wireless technology, Radio transceivers, Low-power design

Abstract: Most portable electrical devices today use battery as their power source which increases the weight, cost and form factor of these devices. This project will focus on advancing technologies to develop battery-less integrated circuits and systems. More specifically, an environmentally-friendly, reconfigurable radio frequency (RF) transceiver with an extremely energy-aware attribute will be designed and developed. In the past few decades, the fundamental system architecture of an RF transceiver has seen little change. While there are many innovative designs in the circuit block and subsystem level, there is practically no energy-aware system architecture that enables ultra-low-power consumption without compromising the performance. This is a revolutionary insight that has never been highlighted before. As power saving through sub-threshold design and energy-aware transceiver are cumulative, a theoretical power consumption reduction of 20 times over state-of-the-art RF transceiver is possible. This far exceeds the power reduction of each technology migration which only yields an average of 1.5 times power consumption reduction.

In this project, the student will design and simulate a 2.4GHz radio for ultra-low-power application using EDA tools. Throughout this project, the student is expected to accomplish the following tasks:

  • Literature review;
  • Design of a 2.4GHz radio;
  • Paper publication for the work done.

Students who are interested in the area of IC design are strongly encouraged to apply.

Preliminary Experimental Results

Some preliminary investigations have been performed and the results are very encouraging. A high speed prescaler is an important block in an RF transceiver. It operates at the highest frequency and therefore consumes a large amount of power. As shown in Figure 1, our group has successfully designed and silicon verified a new low-power high-speed TSPC 2/3 prescaler. When compared with existing architectures, the proposed design is capable of achieving a power consumption reduction of at least 7 times [1,2] while operating at a high frequency of 4.5 GHz as shown in Table 1. Based on the insight gained from the analysis, we have totally eliminated the short-circuit power consumption of the prescaler at radio frequency. In addition, redundant operations in the existing prescaler are removed. Measurement results show that a divide-by-32/33 dual modulus prescaler implemented with this novel 2/3 prescaler is capable of operating up to 4.5 GHz with a power consumption of only 1.4mW.

Figure 1: Die Photograph of the proposed TSPC 2/3 prescalers.

Table 1: Comparisons of SUTD’s novel prescaler with existing prescalers

Specifications SUTD’s novel prescaler [1] [2]
Process (μm) 0.18 0.25 0.18
Supply voltage (V) 1.8 2.5 1.8
Power Consumption for Divide-by-2 Operation at 4.5GHz (mW) 0.306 1.875 1.8
Power Consumption for Divide-by-3 Operation at 4.5GHz (mW) 0.461 2.178 1.89

 

References

  1. S. Pellerano, S. Levantino, C. Samori, and A. L. Lacaita, “A 13.5-mW 5 GHz frequency synthesizer with dynamic-logic frequency divider,” IEEE J. Solid-State Circuits, vol. 39, no. 2, pp. 378-383, Feb. 2004.
  2. X. P. Yu, M. A. Do, W. M. Lim, K. S. Yeo and J. G. Ma, “Design and Optimization of the Extended True Single-Phase Clock-Based Prescaler,” IEEE Trans. on Microwave Theory and Techniques, vol. 54, no. 11, pp. 3828-3835, Nov. 2006.
2020-10-30T14:55:05+00:00