30.202 Design of Intelligent Digital Integrated Circuits and Systems

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30.202 Design of Intelligent Digital Integrated Circuits and Systems examines the device and circuit level optimization of digital building blocks. Topics covered include: MOS device models including Deep Sub-Micron effects; circuit design styles for logic, arithmetic and sequential blocks; estimation and minimization of energy consumption; interconnect models and parasitic; device sizing and logical effort; timing issues (clock skew and jitter) and active clock distribution techniques; memory architectures, circuits (sense amplifiers) and devices; testing of integrated circuits. The course employs extensive use of circuit layout and SPICE in design projects and software labs.

New topics such as machine learning, and cryptography are covered also for system level design.

Pre-Requisite

Prerequisites will be strictly enforced with a grade of at least a Pass.

Course Lead/Main Instructor

Goal

Integrated Circuits Design in our context covers Integrated Circuits analysis and design.  This is an essential course for all engineer where Integrated Circuits is widely used, especially for electrical engineering, computer engineering students, biomedical engineering, mechatronics and etc. It is because miniaturization is required for those engineering product design.

Learning Objectives

  1. Use CAD tools and circuit techniques to design and lay out an entire digital integrated circuit.
  2. Use dynamic or static logic families to design and layout transistor-level designs for digital blocks such as arithmetic units, instruction decoders, or finite-state controllers.
  3. Use system performance metrics (such as speed and power) to decide the implementation of the logic circuits between dynamic and static logic.
  4. Determine upper limits on clock skew for a given digital design and clock rate, and design a clock distribution network that meets those limits.
  5. Know about the design of dynamic and static memory array and the associated sense amplifier.
  6. Know about the causes of power consumption in chip and reduce the power consumption through the design, lay out and optimization process.
  7. Know about fundamental of Deep Learning architecture in Artificial Intelligence based devices implementation.
  8. Use High Level Synthesis technique in System On Chip implementation.

Measurable Outcomes

  1. Design and lay out a complete digital integrated circuit given a high-level description.
  2. Compare the performance (in speed and power) of a functional block implemented in dynamic versus static logic.
  3. Given a transistor-level design of a functional block, optimize the design to minimize power or to improve speed.
  4. Estimate timing delays and power consumption for transistor-level layouts of functional blocks.
  5. Determine noise immunity for a given layout of a dynamic memory cell.
  6. Estimate the clock skew for a given layout of a clock distribution network.
  7. Estimate the power consumption of the IC chip.
  8. Design and implement an Artificial Intelligence device through System On Chip.

Pedagogy

30.202 is a 12 unit subject (5-0-7), which means that the overall weekly time commitment is, on average, approximately 12 hours.  The actual workload will depend on a number of factors, including the ability of design teams to plan and schedule their time efficiently, the scope chosen by design teams, self-study, homework time. Workload comprises participation in Design, Concept, Implement & Operate (2.5 hours per week), Reflection & Interaction (2.5 hours per week) and non-guided project work (7 hours per week, non-assigned contact time, group meetings, lab note and communication preparation) per week.

Text & References

Text

  • CMOS Digital Integrated Circuits: Analysis and Design, 4/e, by Sung-Mo Kang, and Yusuf Leblebici (2015, McGraw-Hill Higher Education; ISBN: 978-0-07-338062-9).
  • Digital Integrated Circuits, 2/e, by Jan M. Rabeay, Anantha Chandrakasan, and Borivoje Nikolic (2003, Pearson; ISBN-10: 0130909963 • ISBN-13: 9780130909961).

Grading

Provide clear breakdown of grading categories and percentages for the course. Consider SUTD’s and EPD’s pedagogical philosophies and approaches, such as 4D Design, active learning, and minimizing straight, passive lectures, as well as SUTD’s mission, vision, and core values.

Assessment Items

Total

Details

Schedule

In-class Assessment

10%

Presentation, Classroom Participation, Leadership

Weekly

Take-home Assessment

15%

Homework

Weekly

Individual / Group Design Project

25%

1-D, 2-D

Midterm Examination

20%

Open book written exam, covers material from Week-1 to Week-5

2 hours

Final Examination

30%

Open book written exam, covers material from Week-8 to Week-12

2 hours

Total

100%

Policies

Assignments will not be accepted/graded after the due date/time. Do not attempt to hand-in late writing assignments.

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2018-07-18T09:35:23+00:00